1. Field of the Invention
This disclosure relates to processor control systems, and, more particularly, to a processing lock-up prevention circuit.
2. Description of the Related Art
Computer systems may experience abnormal behavior stemming from conditions such as endless loops, power surges, software errors, and the like. Watchdog timer circuits are known in the art for automatically detecting and preventing such abnormal activities. For example, in some computer systems with watchdog timer circuits, the watchdog timer circuit continually increments a timer or counter for a programmable number of cycles and waits to receive a reset signal from the computer system.
If the computer system is operating properly, the reset signal is issued to reset the timer or counter of the watchdog timer circuit before the programmed number of cycles are completed, and the reset watchdog timer circuit then resumes incrementing the timer unless and until the reset signal is issued again from the computer system. However, if the reset signal is not issued before the timer completes the programmed number of cycles, the computer system is presumed to be behaving abnormally, such as operating in an endless loop.
After the timer reaches the programmed number of cycles, the watchdog timer circuit then enters a watchdog mode and performs watchdog functions, such as resetting or powering down the computer system or issuing other control commands to control the computer system.
In order to perform the watchdog functions, the watchdog timer circuit is enabled to wait to enter a watchdog mode. A watchdog timer circuit may include a control register and/or a period register for receiving data to control the watchdog timer circuit using, for example, interrupts such as non-maskable interrupts (NMI). Once the watchdog timer circuit enters the watchdog mode, the ability to write to the control and period registers is disabled.
When the computer system is operating in circumstances which may require the watchdog timer circuit to perform in watchdog mode, a failure of the user or the computer system to enable the watchdog timer circuit prior to such circumstances may cause the watchdog timer circuit to enter a hang state or a lock-up condition when the watchdog timer circuit is called upon to enter the watchdog mode. Such a hang state may lock-up the watchdog timer circuit and the computer system as well. A global reset may be required in order to exit the hang state, and the malfunction of the computer system may then be corrected.